1. Technical Field
The present disclosure relates to a low pass RC filter, and to an integrated circuit comprising such a filter.
2. Description of the Related Art
FIG. 1 shows a conventional low pass RC filter F0 comprising a filter input node N1, a filter output node N2, a resistor R, and a capacitor C. The resistor R has a first terminal coupled to node N1, and a second terminal coupled to node N2. The capacitor C has a first terminal (or positive plate) coupled to node N2, and a second terminal (or negative plate) coupled to ground GND. Filter F0 further comprises a first inverting gate IG1 and a second inverting gate IG2. Gate IG1 is coupled on input to a node N0 and on output to node N1, and gate IG2 is coupled on input to node N2 and on output to a node N3. Inverting gates IG1, IG2 are each electrically powered by a voltage +V, and are coupled to ground (not shown in FIG. 1). Furthermore, node N1 receives a first logic signal S1 (filter input signal), and node N2 supplies a second logic signal S2 (filter output signal).
Filter F0 may be implemented in various circuits such as ring oscillators, buses, etc. for diverse applications such as communications and automotive. If the signal at node N1 is at a high voltage value, the capacitor C gradually charges through resistor R at a rate according to a time constant τ (tau). Likewise, if the signal at node N1 is at a low voltage value (grounded), the capacitor C gradually discharges through resistor R according to the same time constant. The time constant is the product of resistance R and capacitance C, such that one time constant τ is equal to the amount of time the capacitor takes to reach 63% of the supply voltage +V. It is well known that the capacitor is fully charged or discharged after a period of 5*τ, and is approximately 50% charged or discharged after a period of ln(2)*τ˜0.7*RC [seconds]. The voltage VC of the capacitor C is equal to the potential difference between its two terminals (or plates).
FIG. 2 shows timing diagrams of the logic signals S0, S1, S2, S3 at nodes N0, N1, N2, N3 as well as the capacitor voltage VC over time t. For the sake of simplicity, it is assumed in the following that the switching time of the inverting gates IG1, IG2 is instantaneous, and that the switching point of inverting gate IG2 is equal to +V/2.
Initially, signal S0 is at a low logic value “0” (ground GND), signal S1 is at a high logic value “+V”, signal S2=+V, and signal S3=0. The positive plate of the capacitor C is coupled to the electrical power supply +V by means of the inverting gate IG1, and the negative plate is grounded. The capacitor is fully charged, such that VC=+V.
At a time t1, the signal S0 switches from 0 to +V and the signal S1=0 on output of gate IG1. The capacitor C is decoupled from the power supply, and begins to discharge from voltage +V to 0. Consequently, the voltage at node N2 begins to decrease from +V. Signal S3 remains at 0.
At a time t2, the decreasing voltage at node N2 crosses the switching point +V/2 of inverting gate IG2, such that the signal S3 switches from 0 to +V on output of gate IG2. The delay between times t1, t2 corresponds to a rise time delay d1 of the filter F0.
At a time t3, the signal S0 switches from +V to 0, and the signal S1 returns to +V. The capacitor C is again coupled to the electrical power supply and begins to charge from 0 to voltage +V. Consequently, the voltage begins to increase at node N2. Signal S3 remains at +V.
At a time t4, the increasing voltage at node N2 crosses the switching point +V/2 of the inverting gate IG2, such that the signal S3 switches from +V to 0 on output of gate IG2. The delay between times t3, t4 corresponds to a fall time delay d2 of the filter F0.
FIG. 2 therefore illustrates the delay of the low pass filter F0 on output in response to a change (low to high, or high to low) occurring at the filter input node N1. Consequently, a pulse of signal S1 applied at the filter input node N1 with a width less than the amount of time during which the voltage at node N2 charges or discharges to the switching point +V/2 from a discharged or charged condition does not cause a logic state change at node N3. As a result, pulses or “glitches” less than the delay d1, d2 (i.e., d=0.7*τ seconds) are filtered out.
As an illustrative example, if a delay d=100 nS is desired, the time constant τ=100/0.7˜140 nS=R*C. For a maximum capacitance of 1 pF of the capacitor C, the resistance of the resistor R is equal to 140 kOhms. When implemented on a semiconductor substrate, the resistance is dependent upon a sheet resistance [Ohms/square]. For a typical sheet resistance of 1 kOhms/square, 140 squares of semiconductor surface area would be used to implement the resistor R. Furthermore, the capacitor C is implemented as two plates parallel to the surface of the semiconductor substrate such that the surface area occupied by the resistor and the capacitor is non-negligible. If it is desired to have an increased delay d, the size of the resistor and capacitor may be preventively large.